It utilizes Verilog models and testbenches to implement fault simulation and test generation algorithms.
Logic BIST basics, test pattern generation, and output response analysis. Digital System Test and Testable Design: Using ...
The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered It utilizes Verilog models and testbenches to implement
A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies. test pattern generation
Scan architectures, RT-level scan design, and Boundary Scan (JTAG).
The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage